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NIOS II Processor Implementation In FPGA: An Application of Data Logging System
[Full Text]
AUTHOR(S)
Ms. Sangita M. Pokale, Ms. K. A. Kulkarni, Prof. S. V. Rode
KEYWORDS
Index Terms:- FPGA CYCLONE III CPLD, NIOS II Soft Core Processor,Picoblaze,SOPC builder.
ABSTRACT
Abstract:- This paper present an application study in data logging device.The new kind of soft-core processor was designed based on NIOS II technology. The device make use of NIOS II processor provided by ALT ERA to be implemented in FPGA.NIOS II is a versatile embedded processor family that presents high performance and has been created for FPGA. Author targets implementation NIOS II soft core processor from Altera FPGA Platform. Also one of the FPGA vendor XILINX, are providing MicroBlaze & PicoBlaze RISC architecture. This is of 32 bit processing architecture. Author has implemented one simple digital circuit design on implementation of 8 bit asynchronous counter along with multiplexed seven segments LED Display Driver. Paper shows comparison on HDL based SOPC designing and usual discrete level hardware designing and testing. For HDL based circuit design Xilinx synthesis tool version 9.1 was used. Also after having success in this implementation author has implemented NIOSII soft core processor using QuartusII 10.1 & SOPC Builder Tool from Altera.
REFERENCES
1) NIOSIIDocumentation: www.altera.com/products/ip/processors/nios2.
2) Quartus II Software information and download. http://www.altera.com/products/software/quartus-ii
3) WikiReference: http://en.wikipedia.org/wiki/Soft_microprocessor.
4) Altera DE0 Board vendor: http://www.terasic.com.tw
5) Tutorials for NIOSII implementation: http://www.doulos.com/content/training/altera_niosII_training.php
6) Application Research of Nios II Technology on Logging Device of Ground:
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5661289
7) Hardware-AcceleratedNIOS-II Implementation of a Turbo Decoder:
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5380477
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