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IJSTR >> Volume 9 - Issue 11, November 2020 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Stability Analysis Of Homo And Hetero-Junction Based TFET SRAMS

[Full Text]

 

AUTHOR(S)

M. Pown, B. Lakshmi

 

KEYWORDS

Band to band tunneling, SRAM, tunnel FET, unidirectional current, noise margins.

 

ABSTRACT

This study explores the stability and power dissipation of the homo and hetero-junction based tunnel field effect transistor (TFET) SRAM cells. Given its unique characteristics such as unidirectional current due to its asymmetric source/drain regions, the SRAM designs are exploited accordingly to prevent unnecessary leakage power. Four SRAM circuit configurations, 6T, 7T, modified 6T and modified 7T are considered in this study. The stability analysis of TFET SRAM cells is characterized by estimating read/write noise margins. The modified 7T TFET SRAM design provides better read/write stability due to the utilization of separate read transistor and Vdd collapse assist during write operation. The SRAM cells employing hetero-TFET shows high power dissipation of 0.42 µW for modified 7T cell due to the higher OFF current of hetero-TFET.

 

REFERENCES

[1] Q. Zhang, W. Zhao, and A. Seabaugh, “Low-Subthreshold-Swing Tunnel Transistors,” IEEE Electron Device Lett., vol. 27, no. 4, pp. 297–300, 2006.
[2] W.Y. Choi, B.G. Park, J.D. Lee, and T.J.K. Liu, “Tunneling Field-Effect Transistors (TFETs) with Subthreshold Swing (SS) Less Than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–745, 2007.
[3] S. Saurabh and M.J. Kumar, “Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis,” Jpn. J. Appl. Phys., vol. 48, p. 064503, 2009.
[4] E.H. Toh et al., “Device design and scalability of a double-gate tunneling field-effect transistor with silicon - germanium source,” Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2593–2597, 2008.
[5] Y. Khatami and K. Banerjee, “Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2752–2761, Nov. 2009.
[6] V. Vijayvargiya, B.S. Reniwal, P. Singh, and S.K. Vishvakarma, “Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications,” Electron. Lett., vol. 52, no. 7, pp. 559–560, 2016.
[7] R. Ranjan, Mallikarjunarao, K.P. Pradhan, and P.K. Sahu, “A comprehensive investigation of silicon film thickness ( TSI ) of nanoscale DG TFET for low power applications,” Adv. Nat. Sci. Nanosci. Nanotechnol., vol. 7, no. 3, p. 035009, 2016.
[8] J. Singh, K. Ramakrishnan, S. Mookerjea, S. Datta, N. Vijaykrishnan, and D. Pradhan, “A novel Si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications,” in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2010, pp. 181–186.
[9] Y. Chen, M. Fan, V.P. Hu, P. Su, and C.-T. Chuang, “Evaluation of stability, performance of ultra-low voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 4, no. 4, pp. 389–399, 2014.
[10] Y. Chen, M. Fan, V.P. Hu, P. Su, and C.-T. Chuang, “Design and Analysis of Robust Tunneling FET SRAM,” IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 1092–1098, 2013.
[11] V. Saripalli, S. Datta, V. Narayanan, and J.P. Kulkarni, “Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design,” in IEEE/ACM International Symposium on Nanoscale Architectures, (NANOARCH), 2011, vol. 1, pp. 45–52.
[12] N. Agrawal, H. Liu, R. Arghavani, V. Narayanan, and S. Datta, “Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance,” IEEE Trans. Electron Devices, vol. 62, no. 6, pp. 1691–1697, 2015.
[13] H. Liu, S. Datta, and V. Narayanan, “Steep Switching Tunnel FET : A Promise to Extend the Energy Efficient Roadmap for Post- CMOS Digital and Analog / RF Applications,” in IEEE International Symposium on Low Power Electronics and Design, 2013, pp. 145–150.
[14] V. Saripalli, D.K. Mohata, S. Mookerjea, S. Datta, and V. Narayanan, “Low power Loadless 4T SRAM cell based on degenerately doped source (DDS) In0.53Ga0.47As Tunnel FETs,” Device Res. Conf. - Conf. Dig. DRC, pp. 101–102, 2010.
[15] A. Makosiej, R.K. Kashyap, A. Vladimirescu, A. Amara, and C. Anghel, “A 32nm tunnel FET SRAM for ultra low leakage,” in IEEE International Symposium on Circuits and Systems, 2012, pp. 2517–2520.
[16] D.H. Morris, U.E. Avci, and I.A. Young, “Variation-Tolerant Dense TFET Memory with Low V MIN Matching Low-Voltage TFET Logic Daniel H . Morris , Uygar E . Avci , Ian A . Young T25,” in 2015 Symposium on VLSI Circuits (VLSI), 2015, pp. T24–T25.
[17] A. Seabaugh and Q. Zhang, “Low-Voltage Tunnel Transistors for beyond CMOS Logic,” Proc. IEEE, vol. 98, no. 12, pp. 2095–2110., 2010.
[18] H. Lu and A. Seabaugh, “Tunnel Field-Effect Transistors: State-of-the-Art,” IEEE J. Electron Devices Soc., vol. 2, no. 4, pp. 44–49, 2014.
[19] H. Liu, V. Saripalli, V. Narayanan, and S. Datta, “http://nanohub.org/resources/21015/download/PennState__III-V__TFET_VerilogAModel_1.0.0_Manual.pdf,” nanoHUB, 2015. .
[20] Y. Lee et al., “Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs),” IEEE Trans. Very Large Scale Integr. Syst., vol. 21, no. 9, pp. 1632–1643, 2013.
[21] S. Datta, R. Bijesh, H. Liu, D. Mohata, and V. Narayanan, “Tunnel Transistors for Energy Efficient Computing,” in IEEE International Reliability Physics Symposium (IRPS), 2013, pp. 6A.3.1–6A.3.7.
[22] V. Saripalli, A. Mishra, S. Datta, and V. Narayanan, “An Energy-Efficient Heterogeneous CMP based on Hybrid TFET-CMOS Cores,” in 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, pp. 729–734.
[23] J. Singh, S.P. Mohanty, and D.K. Pradhan, Robust SRAM designs and analysis. 2013.
[24] J.S. Liu, M.B. Clavel, and M.K. Hudait, “An Energy-Efficient Tensile-Strained Ge / InGaAs TFET 7T SRAM Cell Architecture for Ultralow-Voltage Applications,” pp. 1–8, 2017.
[25] Y.N. Chen et al., “A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance,” in Proceedings of the European Solid-State Device Research Conference, 2012, vol. 3, pp. 157–160.
[26] S. Ahmad, S.A. Ahmad, M. Muqeem, N. Alam, and M. Hasan, “TFET-Based Robust 7T SRAM Cell for Low Power Application,” IEEE Trans. Electron Devices, vol. 66, no. 9, pp. 3834–3840, 2019.