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IJSTR >> Volume 1 - Issue 5, June 2012 Edition

International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616

Design And Analysis of Logic Gates Using Static And Domino Logic Technique

[Full Text]



Permendra Kr. Verma, S. K. Singh, Amit Kumar, Sanjay Singh



Static CMOS, Dynamic CMOS, PMOS, NMOS, Power-Saving Clock, Power-Wasting Glitches, Precharge, Logic Gate.



This paper presents a new design of static and Domino logic using CMOS. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing. It was developed to speed up circuits in Dynamic Logic. They have smaller areas than conventional CMOS logic (as does all Dynamic Logic) and parasitic capacitances are smaller so that higher operating speeds are possible. There are many solutions to the problem of how to cascade dynamic logic gates. One way is Domino Logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a PFET (one of the main goals of Dynamic Logic is to avoid PFETs where possible, due to speed), there are two reasons it works well.



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