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IJSTR >> Volume 2- Issue 5, May 2013 Edition

International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616

VHDL Implementation Of Reconfigurable Crossbar Switch For Binoc Router

[Full Text]



Mr. Ashish Khodwe, Mrs. V. K. Rajput, Prof.C.N.Bhoyar, Prof. Priya M. Nerkar



Index Terms: Interconnection networks, on-chip communication, Reconfigurable, crossbar switch .networks-on-chip (NoCs)



Abstract: Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router crossbar switch. This paper presents implementation of 10x10 reconfigurable crossbar switch (RCS) architecture for Dynamic Self-Reconfigurable BiNoC Architecture for Network On Chip. Its main purpose is to increase the performance, flexibility. This paper presents a VHDL based cycle accurate register transfer level model for evaluating the, Power and Area of reconfigurable crossbar switch in BiNoC architectures. We implemented a parameterized register transfer level design of reconfigurable crossbar switch (RCS) architecture. The design is parameterized on (i) size of packets, (ii) length and width of physical links, (iii) number, and depth of arbiters, and (iv) switching technique. The paper discusses in detail the architecture and characterization of the various reconfigurable crossbar switch (RCS) architecture components. The characterized values were integrated into the VHDL based RTL design to build the cycle accurate performance model. In this paper we show the result of simple 4 x4 as well as 10x10 crossbar switch .The results include VHDL simulation of RCS on ModelSim tool for 4 x4 crossbar switch and Xilinx ISE 13.1 software tool for 10x10 crossbar switch.



[1] S. Charles,”Let’s Route Packets Instead of Wires,” Proc. 6th MIT Conf. 1990, Advance Research in VLSI, pp. 133-138.

[2] L. Benini and G. Micheli, “Networks on Chips: A New SoC Paradigm,” IEEE Computer 35(1) 2002, pp. 70-78.

[3] T. Marescaux, A.Bartic, D.Verkest, S.Vernalde, R. Lauwereins, “Interconnection Networks Enable Fine-Grain Dynamic Multi-Tasking on FPGAs,” FPL, Sep, 2002.

[4] W.Dally, “The J-Machine Network” Proc Intnl Conf on Computer Design. IEEE VLSI in Computer & Processor, Oct 1992, pp 420-423.

[5] K. Mai,” Smart Memories: A Modular Reconfigurable Architecture,” Proc ISCA, June 2000, pp. 161-71.

[6] W. J. Dally and B. Towles, “Route packets, not wires,”in Proceedings of the Design Automation Conference(DAC), Las Vegas, NV, USA, June 18-22 2001.

[7] J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S.W. Keckler, and L. S. Peh, “Research challenges foron-chip interconnection networks,” IEEE Micro, vol.27, no. 5, pp. 96–108, September-October 2007.

[8] Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S.Borkar, “A 5-ghz mesh interconnect for a teraflopsprocessor,” IEEE Micro, pp. 51–61, Sept/Oct 2007.

[9] J. Hu and R. Marculescu, “Application-specific bufferspace allocation for network-on-chip router design,” inProceedings of the IEEE/ACM InternationalConference on Computer Aided Design (ICCAD), SanJose, CA, USA, November 7-11 2004, pp. 354–361.

[10] C. A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan,M. S. Yousif, and C. R. Das, “Vichar: A dynamicvirtual channel regulator for network-on-chip routers,”in Proceedings of the 39th Annual InternationalSymposium on Microarchitecture (MICRO), Orlando,FL, USA, December 9-13 2006, pp. 333–344.

[11] A. K. Kodi, A. Sarathy, and A. Louri, “ideal: Interroutedual-function energy and area-efficient links fornetwork-on-chip (noc) architectures,” in Proceedings ofthe International Symposium on Computer Architecture(ISCA), June 2008, pp. 241–250.

[12] H. S. Wang, L. S. Peh, and S. Malik, “Power-drivendesign of router microarchitectures in on-chipnetworks,” in Proceedings of the 36th AnnualACM/IEEE International Symposium onMicroarchitecture, Washington DC, USA, December03-05 2003, pp. 105–116.

[13] S. E. Dongkook Park, R. Das, A. K. Mishra, Y. Xie, N.Vijaykrishnan, and C. R. Das, “Mira: A multi-layeredon-chip interconnect for router architecture,” inProceedings of the International Symposium onComputer Architecture (ISCA), June 2008, pp. 251–261.

[14] W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Fransisco, USA: Morgan Kaufmann, 2004.

[15] J. Kim, W. Dally, B. Towles, and A. Gupta “Microarchitecture of a high-radix router,” inProceedings of the 32th Annual International Symposium on Computer Architecture (ISCA’05), June2005, pp. 420–431.

[16] Kumar, S.; Jantsch, A.; Soininen, J. P.; Fonsell, M. “A Networkon Chip Architecture and Design Methodology”. In:Computer Society Annual Symposium on VLSI, 2002.

[17] Benini, L.; De Micheli, G. “Powering networks onchips: energy-efficient and reliable interconnect design forSoCs”. In: 14th International Symposium on Systems Synthesis,2001, pp. 33-38.

[18] Guerrier. P.; Greiner. A. “A generic architecture for on-chip packet-switched interconnections”. In: Design Automation and Test in Europe (DATE’00), 2000, pp. 250-256.

[19] D. E. Comer, “Network Systems Design using Network Processors”, Prentice Hall, 2003

[20] D. Kim, K. Lee, S. Lee and H. Yoo, “A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on-Chip”, IEEE International Symposium on Circuits and Systems, 2005, pp. 2369 - 2372

[21] S. Young, et al., “A High I/O Reconfigurable Crossbar Switch”, 11th Annual IEEE Symposium on Field- Programmable Custom Computing Machines, Napa, Califormia, April 09-13, 2003, pp.3-10.

[22] H. C. Freitas and C. A. P. S. Martins, “Didactic Architectures and Simulator for Network Processor Learning”, Workshop on Computer Architecture Education, San Diego, CA, USA, 2003, pp.86-95

[23] T. Farley. TelecomWriting.com’s Telephone History Series. 2001.

[24] L.E.S. Ramos and C.A.P.S. Martins, “A Proposal of Reconfigurable MPI Collective Communication Functions”. Third International Symposium on Parallel and Distributed Processing and Applications, LNCS 3758, Nanjing, China, November 2-5, 2005, pp. 102-107

[25] D. A. Buell, J. M. Arnold, and W. J. Kleinfelder. Splash 2: FPGAs in Custom Computing Machine. IEEE Computer Society Press, Napa Valley, Ca, 1996.

[26] P. Bellows and B. Hutchings. JHDL: An hdl for reconfigurable systems. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 175–184, Napa Valley, Ca, April 1998. IEEE Computer Society.

[27] [ 9] S. A. Guccione and D. Levi. XBI: A java-based interface to FPGA hardware. In J. Schewel, editor, Configurable Computing: Technology and Applications, Proc. SPIE 3526, pages 97–102, Bellingham, WA, November 1998. SPIE – The International Society for Optical Engineering.

[28] J. Chang, S. Ravi, and A. Raghunathan, “FLEXBAR: A crossbar switching fabric with improved performance and utilization”, IEEECustom Integrated Circuits Conference, May 2002, pp.405-408

[29] C. Patterson. High performance des encryption in virtex fpgas using jbits. In K. L. Pocek and J. Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, Ca, April 2000. IEEE Computer Society.

[30] [12] S. P. McMillan and S. A. Guccione. Partial run-time reconfiguration using JRTR. In R. W. Hartenstein and H. Grunbacher, editors, Field-Programmable Logic and Applications, pages 352–360, Berlin, August 2000. Springer-Verlag.

[31] E. Lemoine and D. Merceron. Run time reconfiguration of FPGA for scanning genomic databases. In K. L. Pocek and J. Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pages 90–98, Napa Valley, Ca, April 1995. IEEE Computer Society.

[32] J. Scalera and M. Jones. A run-time reconfigurable plug-in for the winamp mp3 player. In K. L. Pocek and J. Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pages 319–320, Napa Valley, Ca, April 2000. IEEE Computer Society.

[33] J. M. Ditmar. A dynamically reconfigurable FPGA-based content addressable memory for IP characterization. Master’s thesis, KTH-Royal Institute of Technology, Stockholm, Sweden, 2000.

[34] S. A. Guccione, D. Levi, and D. Downs. A reconfigurable content addressable memory. In J. R. et al., editor, Proceedings of the 15th International Parallel and Distributed Processing Workshops, pages 882–889, Berlin, May 2000. Springer-Verlag.

[35] H. Eggers, P. Lysaght, H. Dick, and G. McGregor, “Fast Reconfigurable Crossbar Switching in FPGAs”, Proceedings of 6th International Workshop on Field-Programmable Logic and Applications, Springer LNCS 1142, 1996, pp.297-306

[36] W. J. Dally, "Virtual-channel flow control," in Proceedings of the 17th Annual International Symposium on Computer Architecture (ISCA), pp. 60-68, 1990.

[37] A. A. Chien. A cost and speed model for k-ary n-cube wormhole routers. In Proceedings of Hot Interconnects, 1993.

[38] Ying-Cherng Lan, Hsiao-An Lin, Shih-Hsin Lo, Yu Hen Hu, and Sao-Jie Chen, “A bidirectional noc (binoc) architecture with dynamic selfreconfigurable channel,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, no. 3, pp. 427 –440, march 2011.