International Journal of Scientific & Technology Research

Home About Us Scope Editorial Board Blog/Latest News Contact Us
10th percentile
Powered by  Scopus
Scopus coverage:
Nov 2018 to May 2020


IJSTR >> Volume 2- Issue 4, April 2013 Edition

International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616

A Low-Cost Very Large Scale Integration Architecture For Idct With Sharing Techniques

[Full Text]



S. Shunmugapriya, M. Saravanan



Keywords:- Hardware Share, multiple inverse transform, Video decoding,factor share,adder share.



Abstract:- The intercommunications between the video devices using different standards are so much inconvenient, thus video codec supporting multiple standards are more useful and more attractive. In this brief, a low cost very large scale integration (VLSI) architecture is designed for multistandard inverse Discrete Cosine transform. It is used in multistandard decoder of MPEG-2, MPEG-4 ASP, and VC-1 .Two circuit share strategies, factor share (FS) an adder share (AS) are applied to the inverse transform architecture for saving its circuit resource. Pipelined stages are used in this Multistandard inverse transform to increase the operational speed.



[1]. N. Ahmed, T. Natarajan, and K. R. Rao, “On image processing and adiscrete cosine transform,” IEEE Trans. Comput., vol. C-23, no. 1, pp. 90–93, Jan. 1974.

[2]. S. Lee and K. Cho, “Architecture of transform circuit for video decodersupporting multiple standards,” Electron. Lett., vol. 44, no. 4, pp. 274–275,Feb. 2008.

[3]. N. T. Ngo, T. T. T. Do, T. M. Le, Y. S. Kadam, and A. Bermak, “ASIPcontrolledinverse integer transform for H.264/AVC compression,” in Proc.IEEE/IFIP Int. Symp. Rapid Syst. Prototyping, 2008, pp. 158–164.

[4]. Y. Li, Y. He, and S. L. Mei, “A highly parallel joint VLSI architecture fortransforms in H.264/AVC,” J. Signal Process. Syst., vol. 50, no. 1, pp. 19–32, Jan. 2008.

[5]. C. P. Fan and G. A. Su, “Fast algorithm and low-cost hardware-sharingdesign of multiple integer transforms for VC-1,” IEEE Trans. Circuits Syst.II, Exp. Briefs, vol. 56, no. 10, pp. 788–792, Oct. 2009.

[6]. W. Chen, C. H. Smith, and S. C. Fralick, “A fast computational algorithmfor the discrete cosine transform,” IEEE Trans. Commun., vol. COM-25,no. 9, pp. 1004–1009, Sep. 1977.

[7]. IEEE Standard Specifications for the Implementations of 8 × 8 InverseDiscrete Cosine Transform, IEEE Standard 1180-1990, 1990.

[8]. T. C. Wang, Y. W. Huang, H. C. Fang, and L. G. Chen, “Parallel 4 × 4 2Dtransform and inverse transform architecture for MPEG-4 AVC/H.264,” inProc. IEEE Int. Symp. Circuits Syst., 2003, pp. 800–803.

[9]. H. Qi, Q. Huang, and W. Gao, “A low-cost very large scale integrationarchitecture for multistandard inverse transform,” IEEE Trans. CircuitsSyst. II, Exp. Briefs, vol. 57, no. 7, pp. 551–555, Jul. 2010.

[10]. Coding of Still Pictures, ISO/IEC JTC 1/SC 29/WG 1, 2009.

[11]. Video Coding Standard, Information Technology—Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to About1,5 Mbit/s—Part 2: Video, ISO/IEC 11172-2 MPEG-1, 1993.

[12]. Video Coding Standard, Information technology—Generic Coding ofMoving Pictures and Associated Audio Information: Video, ISO/IEC 13818-2 MPEG-2, 1995

[13]. Video Coding Standard, Information Technology—Coding of Audio-Visual Objects—Part 2: Visual, ISO/IEC 14496-2 MPEG-4, 2004.

[14]. T. Wiegand and G. Sullivan, Draft ITU-T Recommendation and FinalDraft International Standard of Joint Video Specification (ITU-T rec.H.264/ISO/IEC 14496-10 AVC, Presented at Joint Video Team (JVC) ofISO/IEC MPEG and ITU-T VCEG), 2003.