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A 3-Input Lookup Table Based Signed Multiplier For DSP Systems
[Full Text]
AUTHOR(S)
Aneela Pathan, Tayab Din Memon, Fareesa Sohu
KEYWORDS
FPGA, Lookup Table, DSP, Signed Arithmetic, Multiplication, Optimization.
ABSTRACT
FPGA comes with various mounts on DSP modules for direct hardware-based implementations of all arithmetic circuits. Various schemes, for example, of signed and unsigned multipliers on FPGA are observed in research. The problem arises when the large design like network on chip (NOC), or systems on chip (SOC) consumes all available resources and the options remain to completely translate the remaining logic on lookup tables only. This paper proposes the lookup table based architecture for an 8X8 signed multiplier, that consumes no builtin arithmetic models other than the LUTS. The architecture follows the shift and adds a scheme that in usual is unsigned in nature. Besides, the comparison of the proposed multiplier is done with the conventional signed Booth multiplication scheme implemented on arithmetic cores of Spartan-6 FPGA in general, which may further be used for any class of FPGA board. The implementation results show the functional verification of the proposed signed multiplier and also It is concluded that amongst the area speed trade-off, Booth performs well in achieved frequency, whilst consuming a few more look-up tables and no built-in arithmetic core, the proposed architecture also is a suitable choice for large DSP systems.
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